DFT Engineer

We are looking for a highly skilled DFT Engineer with strong expertise in scan architecture, MBIST, ATPG, fault simulation, and silicon test methodologies. The ideal candidate will drive Design-for-Test implementation, verification, and test strategy development for advanced ASIC and SoC designs.

We are looking for a highly skilled DFT Engineer with strong expertise in scan architecture, MBIST, ATPG, fault simulation, and silicon test methodologies. The ideal candidate will drive Design-for-Test implementation, verification, and test strategy development for advanced ASIC and SoC designs.

Location: Ahmedabad / Bangalore

Experience: 3-8 Years

Plan, design, develop, benchmark, and deploy end-to-end DFT strategies for deep submicron ASICs and SoCs.

Perform scan insertion, MBIST insertion, BSCAN implementation, and ATPG generation.

Develop and validate RTL, GLN, and test pattern deliverables.

Collaborate with logic design, physical design, and post-silicon teams to achieve test architecture closure.

Support test-mode STA and physical implementation requirements.

Drive multiple ASIC programs simultaneously while maintaining delivery schedules.

Improve test coverage through architecture and methodology enhancements.

Debug and resolve DFT implementation and timing-related issues.

Coordinate with cross-functional teams to achieve project milestones.

Contribute to DFT methodology improvements and best practices.

Minimum 3 years of dedicated DFT experience.

Strong expertise in JTAG, MBIST, Scan Compression, ATPG, and Fault Simulation.

Hands-on experience with DFT tools such as Synopsys TetraMAX, Mentor FastScan, and Cadence Encounter Test.

Experience with industry-standard simulation tools including VCS, ModelSim, and NC Verilog.

Strong knowledge of SCAN, MBIST, and BSCAN architecture and insertion methodologies.

Deep understanding of test strategies and fault model fundamentals.

Experience with RTL simulation, physical design flows, and post-silicon support.

Ability to debug test-mode timing constraints and resolve related issues.

Experience with power-aware test architecture is highly desirable.

Strong proficiency in scripting languages such as TCL and PERL.

Excellent analytical, debugging, and problem-solving skills.

Ability to work effectively with geographically distributed engineering teams.

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or related field.