Formal Verification Engineer

We are seeking an experienced Formal Verification Engineer to develop and execute formal verification strategies for complex digital designs and SoCs. The ideal candidate will have strong expertise in formal methodologies, assertion-based verification, model checking, scripting, and advanced verification flows to ensure functional correctness and design reliability.

We are seeking an experienced Formal Verification Engineer to develop and execute formal verification strategies for complex digital designs and SoCs. The ideal candidate will have strong expertise in formal methodologies, assertion-based verification, model checking, scripting, and advanced verification flows to ensure functional correctness and design reliability.

Location: Bengaluru

Experience: 4-8 Years

Develop and execute formal verification plans for complex IPs, subsystems, and SoCs.

Create formal verification environments using industry-standard tools and methodologies.

Develop SystemVerilog Assertions (SVA) and PSL-based verification models.

Perform model checking, theorem proving, and property verification activities.

Collaborate with design and verification teams to identify and close functional bugs early in the design cycle.

Analyze verification coverage and improve verification quality.

Automate verification flows using scripting languages and custom tools.

Support verification sign-off activities and documentation.

Drive adoption of formal verification methodologies across projects.

Participate in architecture reviews and verification planning discussions.

4-8 years of experience in Functional Verification, Formal Verification, or Digital Hardware Design.

Strong understanding of formal verification methodologies including SVA, PSL, model checking, and theorem proving.

Knowledge of formal verification applications for functionally safe and automotive-grade IPs is a plus.

Strong understanding of digital design and verification fundamentals.

Understanding of computer architecture and micro-architectural concepts.

Hands-on experience with hardware description and verification languages including VHDL, Verilog, SystemVerilog, and PSL.

Experience using industry-standard formal verification tools.

Understanding of complete end-to-end verification flow from planning to closure.

Proficiency in scripting languages such as Python, Perl, and TCL.

Strong Shell scripting skills.

Knowledge of ARM architecture and instruction sets.

Experience with model checking and formal proof techniques.

Understanding of invariants, abstractions, and state-space reduction techniques.

Knowledge of assume-guarantee reasoning and compositional verification.

Strong debugging, analytical, and problem-solving abilities.

Excellent communication and teamwork skills.