FPGA Engineer

We are seeking a highly motivated FPGA Engineer with strong experience in FPGA prototyping, emulation platforms, RTL verification, and SoC development. The ideal candidate will work on advanced semiconductor projects involving FPGA-based emulation, verification environments, HW/SW co-verification, and system-level debugging.

We are seeking a highly motivated FPGA Engineer with strong experience in FPGA prototyping, emulation platforms, RTL verification, and SoC development. The ideal candidate will work on advanced semiconductor projects involving FPGA-based emulation, verification environments, HW/SW co-verification, and system-level debugging.

Location: Bengaluru / Hyderabad

Experience: 4-10 Years

Work on FPGA prototyping and emulation platforms such as Veloce and Palladium.

Develop and maintain FPGA emulation environments for complex SoC designs.

Perform synthesis, place and route, constraint development, and timing closure.

Debug FPGA and emulation systems using waveform analysis and content debugging tools.

Develop synthesizable models for IP blocks to accelerate emulation deployment.

Participate in SoC architecture and methodology development activities.

Collaborate with design and verification teams throughout the development cycle.

Execute block-level and chip-level verification plans.

Develop and maintain SystemVerilog and UVM verification environments.

Create SystemVerilog Assertions (SVA) for protocol and functional verification.

Support HW/SW co-verification by developing test cases, APIs, and debug infrastructure.

Contribute to continuous improvements in tools, flows, and methodologies.

Perform RTL and system-level debugging for complex semiconductor designs.

Work closely with embedded software teams for integration and validation.

4-10 years of experience in FPGA design, emulation, or verification.

Hands-on experience with FPGA prototyping and emulation platforms such as Veloce and Palladium.

Strong understanding of synthesis, place and route, constraints, and clocking methodologies.

Experience with SoC architectures including CPU, DSP, multimedia, IO, peripherals, DDR, modem, and bus protocols.

Strong debugging skills with the ability to resolve complex design issues.

Experience in full-chip verification from test plan development through tape-out signoff.

Hands-on experience with SystemVerilog, UVM, and SystemVerilog Assertions (SVA).

Experience developing and executing block-level and chip-level verification plans.

Experience with HW/SW co-verification methodologies.

Strong knowledge of RTL design and verification methodologies.

Experience with scripting languages such as Python and TCL.

Experience using industry-standard simulation tools including NC Verilog, VCS, and QuestaSim.

Strong communication skills and ability to work in cross-functional engineering teams.

Self-motivated with a passion for solving challenging technical problems.