Physical Design Engineer

We are looking for an experienced Physical Design Engineer with strong expertise in complete RTL-to-GDSII implementation flows. The ideal candidate should have hands-on experience in floorplanning, placement, CTS, routing, timing closure, physical verification, and signoff activities for advanced semiconductor designs.

We are looking for an experienced Physical Design Engineer with strong expertise in complete RTL-to-GDSII implementation flows. The ideal candidate should have hands-on experience in floorplanning, placement, CTS, routing, timing closure, physical verification, and signoff activities for advanced semiconductor designs.

Location: Bengaluru / Ahmedabad

Experience: 4-8 Years

Drive complete RTL-to-GDSII implementation flow for ASIC and SoC designs.

Perform floorplanning, placement, CTS, routing, and physical optimization activities.

Execute timing closure and physical signoff methodologies.

Develop and maintain power planning strategies and clock distribution networks.

Perform block-level and chip-level physical design implementation.

Handle analog IP integration and block integration activities.

Run and analyze DRC, LVS, and other physical verification checks.

Perform static timing analysis using PrimeTime.

Work with physical design and CAD teams to improve implementation methodologies.

Support flip-chip package integration and advanced packaging technologies.

Collaborate with RTL, verification, and backend teams to resolve implementation issues.

Develop automation scripts to improve design productivity and quality.

Ensure successful tape-out by meeting timing, power, area, and reliability targets.

4-8 years of experience in Physical Design and ASIC implementation.

Strong understanding of the complete RTL-to-GDSII flow.

Hands-on experience in chip-level and/or block-level physical design implementation.

Strong knowledge of floorplanning, placement, CTS, routing, timing closure, DRC, and LVS.

Experience with block integration including analog IP integration.

Hands-on experience with ICC2, PrimeTime, and IC Validator.

Strong understanding of physical verification signoff methodologies.

Knowledge of power planning and clock mesh/conventional CTS architectures.

Exposure to flip-chip package design technologies.

Strong understanding of deep sub-micron IC design methodologies.

Experience with scripting languages such as TCL, Perl, and Python.

Knowledge of CAD automation methodologies is highly desirable.

Excellent analytical, debugging, and problem-solving skills.

Strong communication skills and ability to work with customers and cross-functional teams.

Ability to work independently and handle multiple priorities under tight schedules.

Strong decision-making skills and ability to perform under pressure.