Verification Engineer

We are looking for an experienced Verification Engineer to develop and execute advanced verification environments for complex SoC and IP designs. The ideal candidate will have strong expertise in SystemVerilog, UVM methodology, functional verification, scripting, and verification planning across block-level and chip-level projects.

We are looking for an experienced Verification Engineer to develop and execute advanced verification environments for complex SoC and IP designs. The ideal candidate will have strong expertise in SystemVerilog, UVM methodology, functional verification, scripting, and verification planning across block-level and chip-level projects.

Location: Bengaluru / Noida

Experience: 3-8 Years

Design and verify digital hardware modules using VHDL and Verilog.

Develop verification environments using SystemVerilog and UVM methodology.

Create reusable verification components and methodology-based testbenches.

Develop verification plans for block-level and chip-level verification activities.

Perform functional and code coverage analysis to ensure design quality.

Execute simulation, synthesis, and routing verification flows.

Write and maintain verification scripts using Python, Perl, Bash, and TCL.

Develop SystemVerilog assertions for protocol and functional checks.

Debug RTL and verification environment issues efficiently.

Collaborate with design engineers to identify and resolve functional bugs.

Manage verification deliverables throughout the product lifecycle.

Participate in design reviews and verification sign-off activities.

Maintain verification environments using configuration management tools.

Ensure verification closure through coverage-driven methodologies.

3-8 years of experience in ASIC/SoC verification.

Strong experience with SystemVerilog and UVM methodology.

Hands-on experience in VHDL and Verilog design verification.

Good understanding of simulation, synthesis, and routing flows.

Experience creating methodology-based UVM verification environments from scratch.

Expertise in SystemVerilog assertions and advanced verification techniques.

Strong knowledge of code coverage and functional coverage methodologies.

Experience with scripting languages such as Python, Perl, Bash, and TCL.

Knowledge of SoC architecture and digital design concepts.

Experience using configuration management tools such as Git, SVN, and ClearCase.

Strong debugging, analytical, and problem-solving skills.

Excellent written and verbal communication skills in English.

Experience executing block-level and chip-level verification plans.