Design & Testability Services

Overcome power consumption challenges and huge data volumes in testing.

Design for Testability (DFT) is one of the effective ways to overcome power consumption challenges and huge data volumes in the testing process after production, which has grown dramatically in lower geometry node designs. DFT is becoming a key factor that saves higher design cost, higher power consumption, increasing execution testing time, chip area, pin counts, and other new fault types at small geometries in the testing phase itself.

Our team of highly experienced implementation and Design-for-Test (DFT) engineers use a best-in class design flow that uses either Synopsys IC Compiler II or Cadence Innovus Implementation System for physical design, the Mentor Tessent Suite for DFT, and Mentor Calibre for physical verification and sign-off. Our services range from RTL-to-GDSII block-level implementation for mixed signal analog-on-top design to hierarchical digital design in leading edge nodes.

With the ongoing trend of lower technology nodes, there is an increase in system-on-chip variations like size, threshold voltage and wire resistance. Due to these factors, new models and techniques are introduced to high-quality testing.

ASIC design is complex enough at different stages of the design cycle. Telling the customers that the chips have faults when you are already at the production stage is embarrassing and disruptive. It’s a situation that no engineering team wants to be in. In order to overcome this situation, design for test is introduced with structural techniques such as Scan Path Insertion, Memory BIST, and ATPG.

The semiconductor designs are getting more complex, owing to the need for lower geometries like 28nm, 16nm, 7nm, and beyond, even while the number of I/O pins on the processor increases. As transistor count increases exponentially, it directly impacts the costs involved in enhancing testers, alongside the complex types of test patterns (more logic gates to be tested) applied in multiple test cycles to achieve high test quality.

To limit the use of numbers of pin-counts and testers, alongside a reduction in the overall product cost in a more efficient manner, our DFT engineers turn to modern testability techniques. These apply on a growing number of pin counts and scan patterns seamlessly, leveraging methods like reduced pin-count testing (RPCT).

Scan Path Insertion is deployed as a methodology of linking all register elements into one long shift register (scan path). This allows our testing platforms to isolate and check targeted small components of the design architecture instead of validating the whole monolithic design in a single cycle.

Memory BIST (MBIST) is increasingly vital at lower technology nodes, where chip memory demands reduced area footprint and fast access times. We implement MBIST devices directly to check RAMs, delivering a comprehensive built-in self-test solution to counter memory errors alongside automated self-repair proficiencies.

ATPG (Automated Test Pattern Generation) completes our testing pipeline, creating optimized test vectors and sequential input patterns to accurately parse the structural design for any silicon faults generated within distinct elements of the circuit.